Peter A Beerel

Associate Chair, Computer Engineerng Division

Peter A Beerel is a skilled expert, working in Usc Viterbi School of Engineering as a Associate Chair, Computer Engineerng Division since 2019. This person has earned professional experience in more than nine positions at different companies. Peter A Beerel went to the Stanford University and got education from 1989 to 1994. Van Nuys, California is the area, where this expert was lastly known to be situated. The professional's phone and email are easily accessed through this website on demand.
Name variants:
Petr Beerel, Pete Beerel, Petie Beerel, Petey Beerel

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Contact Information

Last Update
Jul 12, 2022
Email
pa**@usc.edu
Location
Van Nuys, CA

Workplace

USC Viterbi School of Engineering
Associate Chair, Computer Engineerng Division

Industry

Higher Education

Work History

Associate Chair, Computer Engineerng Division

from Jan 2019

Chief Scientist

San Francisco, CA
Our mission is to build ultra energy-efficient hardware using asynchronous bundled-data resilient design tools and techniques developed by my research group at USC. I work at REM one day a w...
Jul 2016 — Dec 2018

Chief Scientist, Technology Development

Santa Clara, CA
2011 — Jul 2015

Chief Executive Officer and Co-Founder

We developed EDA tools and hardware IP that give breakthrough power and performance to the ASIC market. We were bought by Fulcrum Microsystems in 2010.
Apr 2008 — Apr 2010

Faculty Director of Innovation Studies

2006 — 2008

Technical Advisor and Research Collaborator

26630 Agoura Rd, Calabasas, CA 91302
Jun 2000 — Aug 2008

Professor

Los Angeles, CA
Teach and do research in VLSI and CAD.
from Aug 1994

Professor

3740 Mcclintock Ave, Los Angeles, CA 90089

President

26630 Agoura Rd, Calabasas, CA 91302

Education

1989 — 1994

Occupations

Supporting Member
Executive
Chairperson
Scientist
Team Member
Chief Executive

Skills

Asic
Eda
Verilog
Vlsi
Computer Architecture
Vhdl
C
Digital Electronics
Algorithms
Integrated Circuit Design
Simulations
Cmos
Circuit Design
Embedded Systems
Matlab
Hardware Architecture
Cadence Virtuoso
Semiconductors
Perl
Rtl Design
Very Large Scale Integration
Cad
High Performance Computing
Tcl
Soc
Systemverilog
Static Timing Analysis
R&D
Cadence
Spice
Logic Synthesis
Microprocessors
Ic
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