Bhupendra K Ahuja is a skilled expert, working in Synaptics main office of which is in 1300. on the position of Director of Design Engineering from 2019. This expert has earned professional experience in more than 12 positions at various companies. Bhupendra K Ahuja went to the Carleton University and received education. Fremont, California is the city, where this expert was lastly known to be located. The professional's e-mail and phone can be accessed through this website by request.
Name variants:
Bhupendra Ahuja
Contact Information
Last Update
Jul 13, 2022
Email
ba**@yahoo.com, bk**@lycos.com, ah**@home.com
Location
Fremont, CA
Company
Workplace
Director of Design Engineering
San Jose, CA
Industry
Consumer Electronics, Custom-Designed User Interface Solutions and Peripherals, Developer and Supplier of Custom-Designed User Interface Solutions and Peripherals, Mfg Computer Peripheral Equipment Prepackaged Software Services, Mfg Computer Peripheral Equipment, Other Computer Peripheral Equip Mfg, Other Computer Peripheral Equipment Manufacturing
Colleagues
Work History
Distinguished Engineer
San Diego, CA
Designed a 1 Gigabit DSL Modem for CO and CPE applications with direct responsibility of 5.4Gbps SERDES and a 7GHz LCPLL with 140fs jitter for AFE8/IFE8 products.
2014 — 2016
Senior Analog Ic Design Consultant
IC design of high performance LDOs and High speed Drivers (5GHz) in 7nm FF CMOS technology for a leading IP provider. IC design of low power/fast responding LDOs, precision clock generator, ...
from Apr 2014
Director of Mixed Analog Ip Design
2701 San Tomas Expy, Santa Clara, CA 95050
Led Mixed Signal IC design of High Speed Serial Links and Digital PLL in 20nm technology. Active participant of IEEE MIPI committee.
2011 — 2014
Vice President of Analog Design
2309 Bering Dr, San Jose, CA 95131
Led analog IC design team in CA and India to develop 16ch 10Gbps SERDES for BE1 product in 65nm CMOS technologies.
2009 — 2010
Vice President of Analog Design
Led analog design teams in SJ and India to develop 10GBaseT PHY in 40nm CMOS techonology. The chip included 1Gsps 10bit ADC and DAC, 10Gbps KR/XFI and KX4/XAUI Serdes and a 10GHz LC PLL.
2008 — 2009
Director of Engineering
1001 Murphy Ranch Rd, Milpitas, CA 95035
Designed and managed several different Precision Analog products from definition to production:
2003 — 2007
Senior Director of Engineering
Led Design teams for Low Power AFE for CCD/CMOS Digital Imaging and WAN Communications ICs.
1999 — 2002
Director of Engineering
Led a mixed signal design team to provide analog and digital IPs for MPEG2 CODEC, Multiple PLLs, Delta-Sigma ADC and DACs.
1995 — 1998
Design Manager
Joined this startup Graphics Controller company from day 1 with mission of integrating Analog, Digital and Memory in a standard DRAM process.
1993 — 1995
Design Manager
Santa Clara, CA
Project lead for Telecom ICs such as PCM CODEC/Filter and Voiceband Modems. Won Intel Achievement Award for first time Si success on Voiceband Modem AFE. Published/Developed a novel frequenc...
1980 — 1992
Occupations
Executive
Director
Operations Manager
Skills
Mixed Signal
Analog
Ic
Cmos
Analog Circuit Design
Semiconductors
Low Power Design
Pll
Circuit Design
Integrated Circuit Design
Adcs
Soc
Serdes
Power Management
Silicon
Vlsi
Digital Signal Processors
Integrated Circuits
Phase Locked Loop
System on A Chip