Ardeshir Ad Hadaegh
Senior Staff Engineering Program Manager - Artificial Intelligence Plathform
Ardeshir Ad Hadaegh is a high-level professional, working in Marvell Semiconductor main office of which is in 1286. on the position of Senior Staff Engineering Program Manager - Artificial Intelligence Plathform from 2019. Ardeshir Ad Hadaegh has earned professional experience in more than five positions at various companies. Ardeshir Ad Hadaegh went to the Sharif University of Technology and received education. San Francisco, California is the city, where this person was lastly known to be settled. Ardeshir Ad Hadaegh's phone number and email can be accessed through Connexy by request.
Name variants:
Ardeshir Hadaegh
Contact Information
Last Update
Jul 7, 2022
Email
ar**@yahoo.com
Location
San Francisco, CA
Company
Marvell Semiconductor
Workplace
Senior Staff Engineering Program Manager - Artificial Intelligence Plathform
Work History
Senior Staff Engineering Program Manager - Artificial Intelligence Plathform
5488 Marvell Ln, Santa Clara, CA 95054
o Program Leader for AIBU from concept to delivery
o Leading the project core teams that is composed of: technology, supply chain,
platform, product, software, quality and business functi...
from Feb 2019
Director of Architecture and Program Managment
47467 Fremont Blvd, Fremont, CA 94538
Managing
o SoC Architecture
Hands on Specification and Development
o Projects
Staffed around the globe (China, US and European teams)
o 70M
gate SoCs with Quad A53, Multiple MIPs 74K/...
Mar 2010 — Dec 2018
Asic Architect and Project Manager
9605 Scranton Rd SUITE 150, San Diego, CA 92121
Responsible for
o Structure ASIC Architecture Definition and Design
LiquidASIC™ and LiquidASIC Z.
o Leading the Front End Design Team (RTL Development + Verification)
o Technical Suppor...
Dec 2007 — Mar 2010
Senior Asic and System Architect
1320 Ridder Park Dr, San Jose, CA 95131
Responsible for definition of the Highend Media Processors and Mobile Processors. complete definition of the ASIC Architecture. Software modules and System. RTL coding, Verification includin...
Sep 2002 — Dec 2007
Project Lead and Asic Architect
350 Campus Dr, Marlborough, MA 01752
Lead the Architecture and Designs of 3 ASICs very large ASIC (520 mm2) including a high performance Dual 10Gb TOE (TCP/IP Offload Engine). All chip except TOE in production in Rev 0. Include...
Apr 1995 — Sep 2002
Occupations
Executive
Program Director
Leader
Director
Managers
Operations Manager
Skills
Soc
Asic
Fpga
Low Power Design
Program Management
System Architecture
Marketing Strategy
Marketing Management
Engineering Management
Rtl Design
Backend
Design Methodology
Memory Management
Contract Negotiations
Low Power Design
Semiconductors
Embedded Systems
Digital Signal Processors
Contract Negotiation
Ic
Cross Functional Team Leadership
Power Management
Physical Design
Mixed Signal
Logic Synthesis
Integrated Circuit Design
Verilog
Ip
Cmos
Hardware Architecture
Analog
Vlsi
Arm
Microprocessors
Debugging
Dft
Field Programmable Gate Arrays
Integrated Circuits
Internet Protocol
System on A Chip
Application Specific Integrated Circuits
Arm Architecture