Keith Gover

Principle Verification Engineer

With work experience over 21 years, Keith Gover is now working at Andes Technology Corporation based in None as a Principle Verification Engineer. Keith received his education from 1995 to 1997 at the Washington State University. Keith Gover is a qualified expert, that is proven by qualifications : License Clahvws9Wg, License Mfpsvuv6U2, and License 5N7Dmkhqjg. Keith Gover speaks Japanese fluently. This person is located in Portland, Oregon. To contact directly with Keith, you can search for their phone or email or get additional info by requesting access to Keith's further details through Connexy.
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Contact Information

Last Update
Jul 7, 2022
Email
ke**@mentor.com, kg**@xtreme-eda.com
Location
Portland, OR

Workplace

Principle Verification Engineer

Industry

Semiconductors

Work History

Principle Verification Engineer

from Sep 2018

Principal Verification Consultant

Founded in 2002 to offer the highest quality Design and Verification teams available in North America. XtremeEDA has almost 70 full-time engineers on our team with close to 20 years average ...
May 2012 — Sep 2018

Verification Technologist

8005 southwest Boeckman Rd, Wilsonville, OR 97070
Promote the use of Mentor's advanced verification tools and methodology. Assist customers in the use of our tools as well as instructing them in the use of the languages and methodologies ne...
Jan 1999 — May 2012

Design Engineer

Cell library design for new .25um SPARC architecture processor.
Jan 1998 — Jan 1999

Design Engineer

Internship during senior year designing hardware used for compression and encryption of data.
May 1, 1997 — Jan 1, 1998

Education

Occupations

IT Professional
Computer Software Professional
Engineer
Professor
School Principal
Counselor
Sales Specialist
Equipment Tools Purchasing Agent
Executive
Vice President of Sales
Software Developers
School Administrator
Educational Manager
Advisor
Department Store Salesperson
Retail Salesperson
Vice President
Chief Executive

Skills

Eda
Functional Verification
Systemverilog
Open Verification Methodology
Uvm
Simulations
Hardware Architecture
Questa
Tcl
Systemc
Formal Verification
Soc
C
Vhdl
Asic
Mixed Signal
Hardware
Verilog
Rtl Design
Modelsim
Integrated Circuit Design
Static Timing Analysis
Fpga
Cryptography
Python
Application Specific Integrated Circuits
System on A Chip
Field Programmable Gate Arrays
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